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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Rev. 01 -- 28 July 2009 Product data sheet
1. General description
The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter (DAC) with selectable 2x, 4x or 8x interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO). The phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1005D650 also includes a 2x, 4x and 8x clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current.
2. Features
I Dual 10-bit resolution I 650 Msps maximum update rate I I I I I I I I I I IMD3: 79 dBc; fs = 640 Msps; fo = 96 MHz I SFDR: 75 dBc; fdata = 80 MHz; fs = 640 Msps; fo = 19 MHz; PLL on Selectable 2x, 4x or 8x interpolation I Typical 0.95 W power dissipation at 4x filters interpolation Input data rate up to 160 Msps I Power-down and Sleep modes Very low noise cap-free integrated PLL I Differential scalable output current from 1.6 mA to 20 mA 32-bit programmable NCO frequency I On-chip 1.25 V reference Dual-port or Interleaved data modes I External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies I Internal digital offset control LVDS compatible clock I Inverse (sin x) / x function Two's complement or binary offset I Fully compatible SPI port data format 3.3 V CMOS input buffers I Industrial temperature range from -40 C to +85 C
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
3. Applications
I I I I I I I Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information Package Name DAC1005D650HW/C1 HTQFP100 Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad Version SOT638-1 Type number
DAC1005D650_1
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Product data sheet
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5. Block diagram
Product data sheet Rev. 01 -- 28 July 2009 3 of 41
DAC1005D650_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
SDO SDIO 62
SCS_N SCLK 65 64 NCO cos sin
mixer
63 SPI
10-BIT OFFSET CONTROL 10-BIT GAIN CONTROL +
2 AUXILIARY DAC 3
AUXAP AUXAN
DAC1005D650
18 to 25, 28, 29 I0 to I9
10
FIR1 LATCH I 2x
FIR2 2x
FIR3 2x
mixer
90 A x sin x + DAC 91
IOUTAP IOUTAN
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
-
68 dual port/ interleaved data modes FIR1 41, 42 45 to 48, 51 to 54 Q0 to Q9
10
OFFSET CONTROL FIR2 2x FIR3 2x
mixer
REFERENCE BANDGAP
VIRES GAPOUT
69
LATCH Q
2x
+ B + x sin x
+ DAC
86 85
IOUTBP IOUTBN
CLKP CLKN
8 9 CLOCK GENERATOR/ PLL
mixer
10-BIT GAIN CONTROL COMPLEX MODULATOR 74 AUXILIARY DAC 73
DAC1005D650
10-BIT OFFSET CONTROL
AUXBP AUXBN
001aak158
66 RESET_N
Fig 1.
Block diagram
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
6. Pinning information
6.1 Pinning
99 VDDA(1V8) 97 VDDA(1V8) 95 VDDA(1V8) 93 VDDA(1V8) 83 VDDA(1V8) 81 VDDA(1V8) 79 VDDA(1V8) 77 VDDA(1V8) 85 IOUTBN 91 IOUTAN
90 IOUTAP
100 AGND
86 IOUTBP
94 AGND
89 AGND
87 AGND
84 AGND
82 AGND
98 AGND
96 AGND
92 AGND
80 AGND
78 AGND
VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(1V8) AGND CLKP CLKN
1 2 3 4 5 6 7 8 9
76 AGND
88 n.c.
75 VDDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 VDDA(1V8) 70 VDDA(1V8) 69 GAPOUT 68 VIRES 67 d.n.c. 66 RESET_N 65 SCS_N 64 SCLK
AGND 10 VDDA(1V8) 11 d.n.c. 12 d.n.c. 13 TM1 14 TM0 15 VDD(IO)(3V3) 16 GNDIO 17 I9 18 I8 19 I7 20 I6 21 I5 22 I4 23 I3 24 I2 25 AGND
DAC1005D650HW
63 SDIO 62 SDO 61 TM3 60 VDD(IO)(3V3) 59 GNDIO 58 n.c. 57 n.c. 56 n.c. 55 n.c. 54 Q0 53 Q1 52 Q2 51 Q3
VDDD(1V8) 26
DGND 27
I1 28
I0 29
n.c. 30
n.c. 31
VDDD(1V8) 32
DGND 33
n.c. 34
n.c. 35
VDDD(1V8) 36
DGND 37
TM2 38
DGND 39
VDDD(1V8) 40
Q9/SELIQ 41
Q8 42
DGND 43
VDDD(1V8) 44
Q7 45
Q6 46
Q5 47
Q4 48
DGND 49
VDDD(1V8) 50
001aak159
Fig 2.
Pin configuration
DAC1005D650_1
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Product data sheet
Rev. 01 -- 28 July 2009
4 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
6.2 Pin description
Table 2. Symbol VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(1V8) AGND CLKP CLKN AGND VDDA(1V8) d.n.c. d.n.c. TM1 TM0 VDD(IO)(3V3) GNDIO I9 I8 I7 I6 I5 I4 I3 I2 VDDD(1V8) DGND I1 I0 n.c. n.c. VDDD(1V8) DGND n.c. n.c. VDDD(1V8) DGND TM2 DGND
DAC1005D650_1
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Type[1] P O O G P P G I I G P I/O I/O P G I I I I I I I I P G I I I I P G I I P G G Description analog supply voltage 3.3 V auxiliary DAC B output current complementary auxiliary DAC B output current analog ground analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground clock input complementary clock input analog ground analog supply voltage 1.8 V do not connect do not connect test mode 1 (to connect to DGND) test mode 0 (to connect to DGND) input/output buffers supply voltage 3.3 V input/output buffers ground I data input bit 9 (MSB) I data input bit 8 I data input bit 7 I data input bit 6 I data input bit 5 I data input bit 4 I data input bit 3 I data input bit 2 digital supply voltage 1.8 V digital ground I data input bit 1 I data input bit 0 (LSB) not connected not connected digital supply voltage 1.8 V digital ground not connected not connected digital supply voltage 1.8 V digital ground test mode 2 (to connect to DGND) digital ground
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Product data sheet
Rev. 01 -- 28 July 2009
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Pin description ...continued Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Type[1] P I I G P I I I I G P I I I I I I I I G P I/O O I/O I I I I/O I/O P P G O O P G P G P Description digital supply voltage 1.8 V Q data input bit 9 (MSB) select IQ Q data input bit 8 digital ground digital supply voltage 1.8 V Q data input bit 7 Q data input bit 6 Q data input bit 5 Q data input bit 4 digital ground digital supply voltage 1.8 V Q data input bit 3 Q data input bit 2 Q data input bit 1 Q data input bit 0 (LSB) not connected not connected not connected not connected input/output buffers ground input/output buffers supply voltage 3.3 V test mode 3 (to connect to DGND) SPI data output SPI data input/output SPI clock SPI chip select (active LOW) general reset (active LOW) do not connect DAC biasing resistor bandgap input/output voltage analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground complementary auxiliary DAC B output current auxiliary DAC B output current analog supply voltage 3.3 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V
(c) NXP B.V. 2009. All rights reserved.
Table 2. Symbol VDDD(1V8) Q9/SELIQ Q8 DGND VDDD(1V8) Q7 Q6 Q5 Q4 DGND VDDD(1V8) Q3 Q2 Q1 Q0 n.c. n.c. n.c. n.c. GNDIO VDD(IO)(3V3) TM3 SDO SDIO SCLK SCS_N RESET_N d.n.c. VIRES GAPOUT VDDA(1V8) VDDA(1V8) AGND AUXBN AUXBP VDDA(3V3) AGND VDDA(1V8) AGND VDDA(1V8)
DAC1005D650_1
Product data sheet
Rev. 01 -- 28 July 2009
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Pin description ...continued Pin 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 H[2] Type[1] G P G P G O O G G O O G P G P G P G P G G Description analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground complementary DAC B output current DAC B output current analog ground not connected analog ground DAC A output current complementary DAC A output current analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog ground
Table 2. Symbol AGND VDDA(1V8) AGND VDDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND VDDA(1V8) AGND VDDA(1V8) AGND VDDA(1V8) AGND VDDA(1V8) AGND AGND
[1]
P = power supply G = ground I = input O = output. H = heatsink (exposed die pad to be soldered).
[2]
DAC1005D650_1
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Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA(3V3) VDDA(1V8) VDDD(1V8) VI Parameter analog supply voltage (3.3 V) analog supply voltage (1.8 V) digital supply voltage (1.8 V) input voltage pins CLKP, CLKN, VIRES and GAPOUT referenced to AGND pins I9 to I0, Q9 to Q0, SDO, SDIO, SCLK, SCS_N and RESET_N referenced to GNDIO VO output voltage pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to AGND Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 Max +4.6 +4.6 +3.0 +3.0 +3.0 +4.6 +4.6 Unit V V V V V V V VDD(IO)(3V3) input/output supply voltage (3.3 V)
Tstg Tamb Tj
storage temperature ambient temperature junction temperature
-55 -45 -
+150 +85 125
C C C
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 19.8 7.7
Unit K/W K/W
In compliance with JEDEC test board, in free air.
DAC1005D650_1
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Product data sheet
Rev. 01 -- 28 July 2009
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
9. Characteristics
Table 5. Characteristics VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on; unless otherwise specified. Symbol VDD(IO)(3V3) VDDA(3V3) VDDA(1V8) VDDD(1V8) IDD(IO)(3V3) IDDA(3V3) IDDD(1V8) IDDA(1V8) IDDD Ptot Parameter input/output supply voltage (3.3 V) analog supply voltage (3.3 V) analog supply voltage (1.8 V) digital supply voltage (1.8 V) input/output supply current (3.3 V) analog supply current (3.3 V) digital supply current (1.8 V) analog supply current (1.8 V) digital supply current total power dissipation fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO on for x / (sin x) function only fo = 19 MHz; fs = 320 Msps; 4x interpolation; NCO off; DAC B off fo = 19 MHz; fs = 320 Msps; 4x interpolation; NCO off fo = 19 MHz; fs = 320 Msps; 4x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO off fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO on; all VDD fo = 19 MHz; fs = 640 Msps; 8x interpolation; NCO low power on Power-down mode full power-down; all VDD DAC A and DAC B Sleep mode; 8x interpolation; NCO on I I 0.08 0.88 0.13 W W Conditions Test[1] I I I I I I I I I C Min 3.0 3.0 1.7 1.7 Typ 3.3 3.3 1.8 1.8 5 48 270 330 67 0.53 Max 3.6 3.6 1.9 1.9 13 26 309 358 Unit V V V V mA mA mA mA mA W
C C C I
-
0.82 0.94 0.95 1.18
1.4
W W W W
C
-
1.07
-
W
DAC1005D650_1
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Product data sheet
Rev. 01 -- 28 July 2009
9 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on; unless otherwise specified. Symbol Vi Vidth Ri Ci VIL VIH IIL IIH Parameter CLKN)[2] CLKP; or CLKN |Vgpd| < 50 mV |Vgpd| < 50 mV C C D D C C VIL = 1.0 V VIH = 2.3 V I I
[3] [3]
Conditions
Test[1]
Min 825 -100 -
Typ 10 0.5
Max 1575 +100 1.0
Unit mV mV M pF V
Clock inputs (CLKP and
input voltage input differential threshold voltage input resistance input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current full-scale output current output voltage output resistance output capacitance DAC monotonicity offset error variation gain error variation reference output voltage reference output voltage variation reference output current
Digital inputs (I0 to I13, Q0 to Q13) GNDIO 2.3 40 80
VDD(IO)(3V3) V A A
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N) VIL VIH IIL IIH C C VIL = 1.0 V VIH = 2.3 V I I GNDIO 2.3 20 20 1.0 V
VDD(IO)(3V3) V nA nA
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN) IO(fs) VO Ro Co NDAC(mono) EO EG VO(ref) VO(ref) IO(ref) register value = 00h default register compliance range C C C D D guaranteed D C C Tamb = 25 C I C external voltage 1.25 V D 1.8 1.2 1.6 20 250 3 8 6 18 1.25 117 40 VDDA(3V3) 1.29 mA mA V k pF bit ppm/C ppm/C V ppm/C A
Reference voltage output (GAPOUT)
DAC1005D650_1
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Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on; unless otherwise specified. Symbol IO(aux) VO(aux) Parameter Conditions Test[1] I C D Min 0 Typ 2.2 10 Max 2 Unit mA V bit Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) auxiliary output current differential outputs auxiliary output voltage compliance range guaranteed
NDAC(aux)mono auxiliary DAC monotonicity Input timing (see Figure 10) fdata tw(CLK) th(i) tsu(i) Output timing fs ts fNCO fstep fNCO fstep SFDR sampling frequency settling time NCO frequency step frequency NCO frequency step frequency spurious-free dynamic range data rate CLK pulse width input hold time input set-up time
Dual-port mode input
C C C C C
1.5 1.1 1.1 -
20 0 640
160 Tdata - 1.5 650 -
MHz ns ns ns Msps ns MHz MHz Hz MHz MHz MHz
to 0.5 LSB register value = 00000000h register value = FFFFFFFFh
D D D D
NCO frequency range; fs = 640 Msps
0.149 0 620 20 -
Low-power NCO frequency range; fDAC = 640 MHz register value = 00000000h register value = F8000000h Dynamic performance; PLL on fdata = 80 MHz; fs = 320 Msps; B = fdata / 2 fo = 35 MHz at 0 dBFS fdata = 80 MHz; fs = 640 Msps; B = fdata / 2 fo = 4 MHz at 0 dBFS fo = 19 MHz at 0 dBFS fdata = 160 MHz; fs = 640 Msps; B = fdata / 2 fo = 70 MHz at 0 dBFS C 82 dBc I I 76 75 dBc dBc C 82 dBc D D D
DAC1005D650_1
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Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = -40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL on; unless otherwise specified. Symbol SFDRRBW Parameter restricted bandwidth spurious-free dynamic range Conditions fs = 640 Msps; fo = 96 MHz at 0 dBFS 2.51 MHz foffset 2.71 MHz; I B = 30 kHz 2.71 MHz foffset 3.51 MHz; I B = 30 kHz 3.51 MHz foffset 4 MHz; B = 30 kHz 4 MHz foffset 40 MHz; B = 1 MHz IMD3 third-order intermodulation distortion fs = 320 Msps; 4x interpolation fo1 = 49 MHz; fo2 = 51 MHz fo1 = 95 MHz; fo2 = 97 MHz fs = 640 Msps; 8x interpolation fo1 = 95 MHz; fo2 = 97 MHz ACPR adjacent channel power ratio fdata = 76.8 MHz; fs = 614.4 Msps; fo = 96 MHz 1 carrier; B = 5 MHz 2 carriers; B = 10 MHz 4 carriers; B = 20 MHz fdata = 153.6 MHz; fs = 614.4 Msps; fo = 115.2 MHz 1 carrier; B = 5 MHz 2 carriers; B = 10 MHz 4 carriers; B = 20 MHz fdata = 153.6 MHz; fs = 614.4 Msps; fo = 153.6 MHz 1 carrier; B = 5 MHz 2 carriers; B = 10 MHz 4 carriers; B = 20 MHz NSD noise spectral density fs = 640 Msps; 8x interpolation; fo = 19 MHz at 0 dBFS noise shaper disabled noise shaper enabled
[1] [2] [3] [4]
Test[1]
Min
Typ
Max
Unit
-
-89 -88 -89 -83
-83 -81 -67
dBc dBc dBc dBc
I I
C C I
[4] [4]
67 -
81 80 79 77
-
dBc dBc dBc dBc
[4] [4]
fo1 = 152 MHz; fo2 = 154 MHz C
I C C
-
64 61 60
-
dB dB dB
C C C
-
67 63 60
-
dB dB dB
C C C
-
65 63 60
-
dB dB dB
C C
-
-138 -139
-
dBm/Hz dBm/Hz
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 and 120 should be connected across the pins (see Figure 8). |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground. IMD3 rejection with -6 dBFS/tone.
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10. Application information
10.1 General description
The DAC1005D650 is a dual 10-bit DAC operating at up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary weighted sub-DAC. With an input data rate of up to 160 MHz, and a maximum output sampling rate of 650 Msps, the DAC1005D650 allows more flexibility for wide bandwidth and multi-carrier systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1005D650 simplifies the frequency selection of the system. This is also possible because of the 2x, 4x and 8x interpolation filters that remove undesired images. Two modes are available for the digital input. In the Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 20 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are embedded features which provide analog offset correction (internal auxiliary DACs), digital offset control and gain adjustment. All the functions can be set using a SPI. The DAC1005D650 operates at both 3.3 V and 1.8 V using separate digital and analog power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.
10.2 Serial interface (SPI)
10.2.1 Protocol description
The DAC1005D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select bar. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with between 2 to 5 bytes, depending on the content of the instruction byte (see Table 7).
DAC1005D650_1
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Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
RESET_N (optional) SCS_N
SCLK
SDIO SDO (optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
001aaj812
R/W indicates the mode access (see Table 6).
Fig 3.
SPI protocol Table 6. R/W 0 1 Read or Write mode access description Description Write mode operation Read mode operation
In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte.
Table 7. N1 0 0 1 1 Number of bytes to be transferred N0 0 1 0 1 Number of bytes 1 byte transferred 2 bytes transferred 3 bytes transferred 4 bytes transferred
A0 to A4 indicates which register is being addressed. In the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in decreasing order according to Table 9 "Register allocation map".
10.2.2 SPI timing description
SPI can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4.
tw(RESET_N) RESET_N (optional) SCS_N 50 % tsu(SCS_N) 50 % tw(SCLK) SCLK 50 % th(SCS_N)
SDIO
50 % th(SDIO) tsu(SDIO)
001aaj813
Fig 4.
SPI timing diagram
DAC1005D650_1
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Product data sheet
Rev. 01 -- 28 July 2009
14 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
The SPI timing characteristics are given in Table 8.
Table 8. Symbol fSCLK tw(SCLK) tsu(SCS_N) th(SCS_N) tsu(SDIO) th(SDIO) tw(RESET_N) SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Min 30 20 20 10 5 30 Typ Max 15 Unit MHz ns ns ns ns ns ns
10.2.3 Detailed descriptions of registers
An overview of the details for all registers is provided in Table 9.
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Product data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 01 -- 28 July 2009
(c) NXP B.V. 2009. All rights reserved. DAC1005D650_1
NXP Semiconductors
Table 9.
Register allocation map R/W Bit definition b7 b6 SPI_RST NCO_LP_ SEL b5 CLK_SEL INV_SIN_ SEL PLL_DIV_ PD b4 b3 MODE_ SEL b2 CODING b1 IC_PD b0 GAP_PD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DAC_A_PD R/W R/W DAC_A_ SLEEP 3W_SPI NCO_ON PLL_PD Default Bin Hex Dec 128 135 16 102 102 102 38 0 0 10000000 80 10000111 87
Address Register name 0 1 2 3 4 5 6 7 8 9 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h COMMon TXCFG PLLCFG FREQNCO_LSB FREQNCO_LISB FREQNCO_UISB FREQNCO_MSB PHINCO_LSB PHINCO_MSB DAC_A_Cfg_1
MODULATION[2:0] PLL_DIV[1:0] FREQ_NCO[7:0] FREQ_NCO[15:8] FREQ_NCO[23:16] FREQ_NCO[31:24] PH_NCO[7:0] PH_NCO[15:8]
INTERPOLATION[1:0]
PLL_PHASE[1:0]
PLL_POL 00010000 10 01100110 66 01100110 66 01100110 66 00100110 26 00000000 00 00000000 00
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
DAC_A_OFFSET[2:0]
-
-
-
00000000 00 01000000 40 11000000 C0
0 64 192 0 64 192 0 ... 128 0 128 0
10 0Ah DAC_A_Cfg_2 11 0Bh DAC_A_Cfg_3 12 0Ch DAC_B_Cfg_1 13 0Dh DAC_B_Cfg_2 14 0Eh DAC_B_Cfg_3 15 0Fh ... ... DAC_Cfg ...
DAC_A_GAIN_ COARSE[1:0] DAC_A_GAIN_ COARSE[3:2] DAC_B_ SLEEP
DAC_A_GAIN_FINE[5:0] DAC_A_OFFSET[8:3] DAC_B_OFFSET[2:0] -
R/W DAC_B_PD R/W R/W R/W ... R/W R/W R/W R/W AUX_B_PD AUX_A_PD
00000000 00 01000000 40 11000000 C0
DAC_B_GAIN_ COARSE[1:0] DAC_B_GAIN_ COARSE[3:2] ... ... ... ... -
DAC_B_GAIN_FINE[5:0] DAC_B_OFFSET[8:3] ... ... MINUS_ 3DB ... NOISE_ SHPER ...
DAC1005D650
00000000 00 ... ...
26 1Ah DAC_A_Aux_MSB 27 1Bh DAC_A_Aux_LSB 28 1Ch DAC_B_Aux_MSB 29 1Dh DAC_B_Aux_LSB
AUX_A[9:2] AUX_A[1:0] AUX_B[1:0] AUX_B[9:2]
10000000 80 00000000 00 10000000 80 00000000 00
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10.2.4 Registers detailed description
Please refer to Table 9 for a register overview and their default values. In the following tables, all default results are shown highlighted.
Table 10. COMMon register (address 00h) bit description Default settings are shown highlighted. Bit 7 Symbol 3W_SPI Access Value Description R/W 0 1 6 SPI_RST R/W 0 1 5 CLK_SEL R/W 0 1 3 MODE_SEL R/W 0 1 2 CODING R/W 0 1 1 IC_PD R/W 0 1 0 GAP_PD R/W 0 1 serial interface bus type 4 wire SPI 3 wire SPI serial interface reset no reset performs a reset on all registers except 00h data input latch at CLK rising edge at CLK falling edge input data mode dual-port interleaved coding binary two's compliment power-down disabled all circuits (digital and analog, except SPI) are switched off internal bandgap power-down power-down disabled internal bandgap references are switched off
Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit 7 Symbol NCO_ON Access Value Description R/W 0 1 6 NCO_LP_SEL R/W 0 1 NCO disabled (the NCO phase is reset to 0) enabled low-power NCO disabled NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 11. TXCFG register (address 01h) bit description ...continued Default settings are shown highlighted. Bit Symbol Access Value Description R/W 000 001 010 011 100 1 to 0 INTERPOLATION[1:0] R/W 01 10 11 modulation dual DAC: no modulation positive upper single sideband up-conversion positive lower single sideband up-conversion negative upper single sideband up-conversion negative lower single sideband up-conversion interpolation fs = 2fclk fs = 4fclk fs = 8fclk 4 to 2 MODULATION[2:0]
Table 12. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit 7 Symbol PLL_PD Access R/W 0 1 5 PLL_DIV_PD R/W 0 1 4 to 3 PLL_DIV[1:0] R/W 00 01 10 2 to 1 PLL_PHASE[1:0] R/W 00 01 10 0 PLL_POL R/W 0 1 Table 13. Bit 7 to 0 Value Description PLL switched on switched off PLL divider switched on switched off PLL divider factor fs = 2 x fclk fs = 4 x fclk fs = 8 x fclk PLL phase shift of fs 0 120 240 DAC clock edge normal inverted
FREQNCO_LSB register (address 03h) bit description Access Value Description R/W lower 8 bits for the NCO frequency setting
Symbol FREQ_NCO[7:0]
Table 14. Bit 7 to 0
FREQNCO_LISB register (address 04h) bit description Access Value Description R/W lower intermediate 8 bits for the NCO frequency setting
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Symbol FREQ_NCO[15:8]
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
FREQNCO_UISB register (address 05h) bit description Access Value Description R/W upper intermediate 8 bits for the NCO frequency setting
Table 15. Bit 7 to 0
Symbol FREQ_NCO[23:16]
Table 16. Bit 7 to 0
FREQNCO_MSB register (address 06h) bit description Access Value Description R/W most significant 8 bits for the NCO frequency setting
Symbol FREQ_NCO[31:24]
Table 17. Bit 7 to 0
PHINCO_LSB register (address 07h) bit description Access Value Description R/W lower 8 bits for the NCO phase setting
Symbol PH_NCO[7:0]
Table 18. Bit 7 to 0
PHINCO_MSB register (address 08h) bit description Access Value Description R/W most significant 8 bits for the NCO phase setting
Symbol PH_NCO[15:8]
Table 19. DAC_A_Cfg_1 register (address 09h) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_A_PD Access Value Description R/W 0 1 6 DAC_A_SLEEP R/W 0 1 5 to 3 DAC_A_OFFSET[2:0] R/W DAC A power on off DAC A Sleep mode disabled enabled lower 3 bits for the DAC A offset
Table 20. Bit 7 to 6 5 to 0
DAC_A_Cfg_2 register (address 0Ah) bit description Access Value Description least significant 2 bits for the DAC A gain setting for coarse adjustment the 6 bits for the DAC A fine adjustment gain setting
Symbol
DAC_A_GAIN_COARSE[1:0] R/W DAC_A_GAIN_FINE[5:0] R/W
Table 21. Bit 7 to 6 5 to 0
DAC_A_Cfg_3 register (address 0Bh) bit description Access Value Description most significant 2 bits for the DAC A gain setting for coarse adjustment most significant 6 bits for the DAC A offset
Symbol
DAC_A_GAIN_COARSE[3:2] R/W DAC_A_OFFSET[8:3] R/W
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_B_PD Access Value Description R/W 0 1 6 DAC_B_SLEEP R/W 0 1 5 to 3 DAC_B_OFFSET[2:0] R/W DAC B power on off DAC B Sleep mode disabled enabled lower 3 bits for the DAC B offset
Table 23. Bit 7 to 6 5 to 0
DAC_B_Cfg_2 register (address 0Dh) bit description Access Value Description less significant 2 bits for the DAC B gain setting for coarse adjustment the 6 bits for the DAC B gain setting for fine adjustment
Symbol
DAC_B_GAIN_COARSE[1:0] R/W DAC_B_GAIN_FINE[5:0] R/W
Table 24. Bit 7 to 6 5 to 0
DAC_B_Cfg_3 register (address 0Eh) bit description Access Value Description most significant 2 bits for the DAC B gain setting for coarse adjustment most significant 6 bits for the DAC B offset
Symbol
DAC_B_GAIN_COARSE[3:2] R/W DAC_B_OFFSET[8:3] R/W
Table 25. DAC_Cfg register (address 0Fh) bit description Default settings are shown highlighted. Bit 1 Symbol MINUS_3DB Access Value R/W 0 1 0 NOISE_SHPER R/W 0 1 Table 26. Bit 7 to 0 Description NCO gain unity -3 dB noise shaper disabled enabled
DAC_A_Aux_MSB register (address 1Ah) bit description Access Value R/W Description most significant 8 bits for the auxiliary DAC A
Symbol AUX_A[9:2]
Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_A_PD Access Value R/W 0 1 1 to 0
DAC1005D650_1
Description auxiliary DAC A power on off lower 2 bits for the auxiliary DAC A
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AUX_A[1:0]
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
DAC_B_Aux_MSB register (address 1Ch) bit description Access R/W Value Description most significant 8 bits for the auxiliary DAC B
Table 28. Bit 7 to 0
Symbol AUX_B[9:2]
Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_B_PD Access Value R/W 0 1 1 to 0 AUX_B[1:0] R/W Description auxiliary DAC B power on off lower 2 bits for the auxiliary DAC B
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines whether the DAC1005D650 operates in the Dual-port mode or in the Interleaved mode (see Table 30).
Table 30. 0 1 Mode selection Function Dual-port mode (pin Q9) I9 to I0 active Q9 to Q0 active off
Bit 3 setting
Interleaved mode (pin SELIQ) active
10.3.1 Dual-port mode
The data input for Dual-port mode operation is shown in Figure 5 "Dual-port mode". Each DAC has its own independent data input. The data enters the input latch on the rising edge of the internal clock signal and is transferred to the DAC latch.
FIR 1 In LATCH I 2x
FIR 2 2x
FIR 3 2x
FIR 1 Qn LATCH Q 2x
FIR 2 2x
FIR 3 2x
001aaj585
n in Qn = 0 to 9 and for In is 0 to 9.
Fig 5.
Dual-port mode
10.3.2 Interleaved mode
The data input for Interleaved mode operation is shown in Figure 6 "Interleaved mode operation".
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
FIR 1 LATCH I 2x
FIR 2 2x
FIR 3 2x
In FIR 1 Qn/SELIQ LATCH Q 2x FIR 2 2x FIR 3 2x
001aaj586
n in Qn = 9 and for In is 0 to 9.
Fig 6.
Interleaved mode operation
In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, see Figure 6 "Interleaved mode operation" and Figure 7 "Interleaved mode timing (8x interpolation, latch on rising edge)". The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and Q channels.
In SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLKdig Latch I output
N
N+1
N+2
N+3
N+4
N+5
XX
N
N+2
Latch Q output
XX
N+1
N+3
001aaj814
Fig 7.
Interleaved mode timing (8x interpolation, latch on rising edge)
SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse) signal. The first data bits following the SELIQ rising edge are sent in channel I and the following data bits are sent in channel Q. After this, the data is distributed alternately between both channels.
10.4 Input clock
The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see Figure 8) but it can also be interfaced with CML (see Figure 9).
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Z = 50
CLKP
LVDS
Zdiff = 100
LVDS
Z = 50
CLKN
001aah021
Fig 8.
LVDS clock configuration
VDDA(1V8)
1.1 k Z = 50 100 nF
CLKP
55
CML
Zdiff = 100 55 100 nF
LVDS
Z = 50
CLKN
2.2 k
100 nF
AGND
001aah020
Fig 9.
Interfacing CML to LVDS
10.5 Timing
The DAC1005D650 can operate at an update rate (fs) of up to 650 Msps and with an input data rate (fdata) of up to 160 MHz. The input timing is shown in Figure 10 "Input timing diagram".
tsu(i) In/Qn CLK (CLKP-CLKN) 90 % N
th(i) 90 % N+1 N+2
50 % tw(CLK)
001aaj815
n in Qn = 0 to 9 and for In is 0 to 9.
Fig 10. Input timing diagram
The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. In Table 31 "Frequencies", the links between internal and external clocking are defined. The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 12 "PLLCFG register (address 02h) bit description") allows the frequency between the digital part and the DAC core to be adjusted.
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Frequencies CLK input Input data rate (MHz) (MHz) 160 160 80 320 320 160 160 160 80 320 320 160 Interpolation 2x 4x 8x 2x 4x 8x Update rate (Msps) 320 640 640 320 640 640 PLL_DIV[1:0] 01 (/4) 01 (/4) 10 (/8) 00 (/2) 00 (/2) 01 (/4)
Table 31. Mode Dual-port Dual-port Dual-port Interleaved Interleaved Interleaved
The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL (register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This occurs at the input of the DAC core and depends mainly on the sampling frequency. Some examples are given in Table 32 "Sample clock phase and polarity examples".
Table 32. Mode Dual-port Dual-port Dual-port Interleaved Interleaved Interleaved Sample clock phase and polarity examples Input data rate (MHz) 80 80 80 160 160 160 Interpolation 2x 4x 8x 2x 4x 8x Update rate (Msps) 160 320 640 160 320 640 PLL_PHASE [1:0] 01 01 01 01 01 01 PLL_POL 1 0 1 1 0 1
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10.6 FIR filters
The DAC1005D650 integrates three selectable Finite Impulse Response (FIR) filters which enable the device to use interpolation rates of 2x, 4x or 8x. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in Table 33 "Interpolation filter coefficients".
Table 33. Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28)
[1]
Interpolation filter coefficients Second interpolation filter[1] Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) Upper H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Value -2 0 17 0 -75 0 238 0 -660 0 2530 4096 Third interpolation filter[1] Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) Upper H(15) H(14) H(13) H(12) H(11) H(10) H(9) Value -39 0 273 0 -1102 0 4964 8192 Upper H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) Value -4 0 13 0 -34 0 72 0 -138 0 245 0 -408 0 650 0 -1003 0 1521 0 -2315 0 3671 0 -6642 0 20756 32768
First interpolation filter[1]
H(n) is the digital filter coefficient.
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10.7 Quadrature modulator and NCO
The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier signal generated by the Numerically Controlled Oscillator (NCO). The frequency of the NCO is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.
10.7.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M x fs f NCO = ---------------32 2 where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0. (1)
10.7.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: M x fs f NCO = ---------------5 2 where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB. (2)
10.7.3 Minus 3 dB
During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers.
10.8 x / (sin x)
Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 34 "Inversion filter coefficients".
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Inversion filter coefficients Upper H(9) H(8) H(7) H(6) Value 2 -4 10 -35 401
Table 34. Lower H(1) H(2) H(3) H(4) H(5)
[1]
First interpolation filter[1]
H(n) is the digital filter coefficient.
10.9 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current outputs: I O ( fs ) = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O ( fs ) x --------------- 1023- 1023 - DATA I IOUTN = I O ( fs ) x --------------------------------- - 1023 (4) (5) (3)
The setting applied to CODING (register 00h[2]; see Table 9 "Register allocation map") defines whether the DAC1005D650 operates with a binary input or a two's complement input. Table 35 "DAC transfer function" shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 35. Data (Decimal) 0 ... 512 ... 1023 DAC transfer function I9/Q9 to I0/Q0 Binary 00 0000 0000 ... 10 0000 0000 ... 11 1111 1111 Two's complement 10 0000 0000 ... 00 0000 0000 ... 01 1111 1111 0 mA ... 10 mA ... 20 mA 20 mA ... 10 mA ... 0 mA IOUTP IOUTN
10.10 Full-scale current
10.10.1 Regulation
The DAC1005D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor.
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
The reference current is generated using an external resistor of 910 (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs (see Figure 11 "Internal reference configuration").
REF. BANDGAP
100 nF
AGND
910 (1 %)
GAPOUT
AGND
VIRES
DAC CURRENT SOURCES ARRAY
001aaj816
Fig 11. Internal reference configuration
This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 10 "COMMon register (address 00h) bit description").
10.10.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA. It can be further adjusted for each DAC using SPI. The adjustment range is between 1.6 mA to 22 mA 10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 20 "DAC_A_Cfg_2 register (address 0Ah) bit description" and register 0Bh; see Table 21 "DAC_A_Cfg_3 register (address 0Bh) bit description") and to DAC_B_GAIN COARSE[3:0] (register 0Dh; see Table 23 "DAC_B_Cfg_2 register (address 0Dh) bit description" and register 0Eh; see Table 24 "DAC_B_Cfg_3 register (address 0Eh) bit description") define the coarse variation of the full-scale current (see Table 36 "IO(fs) coarse adjustment").
Table 36. IO(fs) coarse adjustment Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal 0 1 2 3 4 5 6 7
DAC1005D650_1
IO(fs) (mA) Binary 0000 0001 0010 0011 0100 0101 0110 0111 1.6 3.0 4.4 5.8 7.2 8.6 10.0 11.4
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 36. IO(fs) coarse adjustment ...continued Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal 8 9 10 11 12 13 14 15 Binary 1000 1001 1010 1011 1100 1101 1110 1111 12.8 14.2 15.6 17.0 18.5 20.0 21.0 22.0 IO(fs) (mA)
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 20 "DAC_A_Cfg_2 register (address 0Ah) bit description") and to DAC_B_GAIN_FINE[5:0] (register 0Dh; see Table 23 "DAC_B_Cfg_2 register (address 0Dh) bit description") define the fine variation of the full-scale current (see Table 37 "IO(fs) fine adjustment").
Table 37. IO(fs) fine adjustment Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal -32 ... 0 ... +31 Two's complement 10 0000 ... 00 0000 ... 01 1111 -10 % ... 0 ... +10 % Delta IO(fs)
The coding of the fine gain adjustment is two's complement.
10.11 Digital offset adjustment
When the DAC1005D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. The settings applied to DAC_A_OFFSET[8:0] (register 09h; see Table 19 "DAC_A_Cfg_1 register (address 09h) bit description" and register 0Bh; see Table 21 "DAC_A_Cfg_3 register (address 0Bh) bit description") and to "DAC_B_OFFSET[8:0]" (register 0Ch; see Table 22 "DAC_B_Cfg_1 register (address 0Ch) bit description" and register 0Eh; see Table 24 "DAC_B_Cfg_3 register (address 0Eh) bit description") define the range of variation of the digital offset (see Table 38 "Digital offset adjustment").
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
Table 38. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[8:0] Decimal -256 -255 ... -1 0 +1 ... +254 +255 Two's complement 1 0000 0000 1 0000 0001 ... 1 1111 1111 0 0000 0000 0 0000 0001 ... 0 1111 1110 0 1111 1111 -256 -255 ... -1 0 +1 ... +254 +255 Offset applied
10.12 Analog output
The DAC1005D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). Refer to Figure 12 for the equivalent analog output circuit of one DAC. This circuit consists of a parallel combination of NMOS current sources, and their associated switches, for each segment.
VDDA(3V3)
RL
RL
IOUTAP/IOUTBP IOUTAN/IOUTBN
AGND
AGND
001aah019
Fig 12. Equivalent analog output circuit (one DAC)
The cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of the DAC by introducing less distortion. The device can provide an output level of up to 2 Vo(p-p) depending on the application, the following stages and the targeted performances.
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DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10.13 Auxiliary DACs
The DAC1005D650 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] define the offset data. I O ( AUX ) = I AUXP + I AUXN The output current depends on the auxiliary DAC data: AUX [ 9:0 ] AUXP = I O ( AUX ) x ------------------------- 1023 (1023 - A UX [ 9:0 ] ) AUXN = I O ( AUX ) x --------------------------------------------- - 1023 Table 39 "Auxiliary DAC transfer function" shows the output current as a function of the auxiliary DAC data.
Table 39. Auxiliary DAC transfer function Default settings are shown highlighted. Data 0 ... 512 ... 1023 AUX_A[9:0] and AUX_B[9:0] (binary) IAUXP 00 0000 0000 ... 10 0000 0000 ... 11 1111 1111 0 mA ... 1.1 mA ... 2.2 mA IAUXN 2.2 mA ... 1.1 mA ... 0 mA
(6)
(7) (8)
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Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10.14 Output configuration
10.14.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 13 "Differential output with transformer; Vo(dif)(p-p) = 1 V"). In addition, it helps to match the impedance and provides electrical isolation.
3.3 V
50 2:1
0 mA to 20 mA IOUTnP 0 mA to 20 mA IOUTnN
50
50
3.3 V IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V
001aaj817
Fig 13. Differential output with transformer; Vo(dif)(p-p) = 1 V
The DAC1005D650 can operate up to 2 Vo(p-p) differential outputs. In this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 14 "Differential output with transformer; Vo(dif)(p-p) = 2 V").
3.3 V
3.3 V
62 4:1
100
0 mA to 20 mA IOUTnP 0 mA to 20 mA IOUTnN
100 50
3.3 V IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V
001aaj818
Fig 14. Differential output with transformer; Vo(dif)(p-p) = 2 V
10.14.2 DC interface to an AQM
When the system operation requires to keep the DC component of the spectrum, the DAC1005D650 can use a DC interface to connect to an Analog Quadrature Modulator (AQM). In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 15 provides an example of a connection to an AQM with a 1.7 V common mode input level.
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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32 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
3.3 V
AQM (Vi(cm) = 1.7 V)
(1)
51.1
51.1 442
(2)
IOUTnP
442
BBP BBN 0 mA to 20 mA
768 768
IOUTnN
(1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V
001aaj541
Fig 15. An example of a DC interface to a 1.7 V AQM
Figure 16 provides an example of a connection to an AQM with a 3.3 Vi(cm) common mode input level.
3.3 V
5V
AQM (Vi(cm) = 3.3 V)
(1)
54.9
54.9 237
750
750
(2)
IOUTnP
237
BBP BBN
1.27 k 1.27 k
IOUTnN
(1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V
001aaj542
Fig 16. An example of a DC interface to a 3.3 V AQM
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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33 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 V common mode input level.
3.3 V
AQM (Vi(cm) = 1.7 V)
(1)
51.1
51.1 442
(2)
IOUTnP
442
BBP BBN 0 mA to 20 mA
698 698
IOUTnN
AUXnP AUXnN 1.1 mA (typ.)
51.1 51.1
(1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 36 mV 001aaj543
Fig 17. An example of a DC interface to a 1.7 Vi(cm) AQM using auxiliary DACs
Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 V common mode input level.
3.3 V
5V
AQM (Vi(cm) = 3.3 V)
(1)
54.9
54.9 237
750
750
(2)
IOUTnP
237
BBP BBN
634 k 634 k
IOUTnN
AUXnP AUXnN
442 k 442 k
(1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV
001aaj544
Fig 18. An example of a DC interface to a 3.3 Vi(cm) AQM using auxiliary DACs
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 28 July 2009
34 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction required.
10.14.3 AC interface to an AQM
When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground, the DAC1005D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 18 provides an example of a connection to an AQM with a 0.5 V common mode input level when using auxiliary DACs.
3.3 V
5V
AQM (Vi(cm) = 0.5 V)
(1)
66.5
66.5 10 nF
2 k
2 k
(2)
IOUTnP
10 nF
BBP BBN 0 mA to 20 mA
174 174
IOUTnN
AUXnP AUXnN 1.1 mA (typ.)
34 34
(1) IOUTnP/IOUTnN; V o(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV
001aaj589
Fig 19. An example of an AC interface to a 0.5 Vi(cm) AQM using auxiliary DACs
10.15 Power and grounding
In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with those on pins 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following pins:
* VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43
and pin 50 with 49.
* VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59. * VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins
79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
* VDDA(3V3): pin 1 with 100 and pin 75 with 76.
DAC1005D650_1
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Product data sheet
Rev. 01 -- 28 July 2009
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
10.16 Alternative parts
The following alternative parts are available.
Table 40. Alternative parts Description dual 12-bit DAC dual 14-bit DAC Sampling frequency up to 650 Msps up to 650 Msps
Type number DAC1205D650 DAC1405D650
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 28 July 2009
36 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
11. Package outline
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c y exposed die pad side X Dh 75 76 51 50 ZE
A
e E HE wM bp pin 1 index Lp L detail X
Eh
A
A2
A1
(A3)
100 1 wM ZD 25 bp D HD
26
e
vM A B vM B
0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD
10 mm
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.08
ZD(1) ZE(1) 1.15 0.85 1.15 0.85
7 0
16.15 16.15 15.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-02-02
Fig 20. Package outline SOT638-1 (HTQFP100)
DAC1005D650_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 28 July 2009
37 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
12. Abbreviations
Table 41. Acronym BB CDMA CML CMOS DAC FIR GSM IF IMD3 LISB LMDS LSB LTE LVDS MMDS MSB NCO NMOS PLL SFDR SPI TD-SCDMA UISB WCDMA WiMAX Abbreviations Description BaseBand Code Division Multiple Access Current Mode Logic Complementary Metal-Oxide Semiconductor Digital-to-Analog Converter Finite Impulse Response Global System for Mobile communications Intermediate Frequency Third-order Inter Modulation Distortion Lower Intermediate Significant Byte Local Multipoint Distribution Service Least Significant Bit Long Term Evolution Low-Voltage Differential Signaling Multichannel Multipoint Distribution Service Most Significant Bit Numerically Controlled Oscillator Negative Metal-Oxide Semiconductor Phase-Locked Loop Spurious-Free Dynamic Range Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Upper Intermediate Significant Byte Wideband Code Division Multiple Access Worldwide Interoperability for Microwave Access
DAC1005D650_1
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Product data sheet
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38 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
13. Glossary
Spurious-Free Dynamic Range (SFDR): -- The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): -- From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined below. IMD2 -- The ratio of the RMS value of either tone to the RMS value of the worst 2nd order intermodulation product. IMD3 -- The ratio of the RMS value of either tone to the RMS value of the worst 3rd order intermodulation product. Restricted Bandwidth Spurious-Free Dynamic Range -- The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise, including the harmonics, in a given bandwidth centered around foffset.
14. Revision history
Table 42. Revision history Release date 20090728 Data sheet status Product data sheet Change notice Supersedes Document ID DAC1005D650_1
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 28 July 2009
39 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1005D650_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
17. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.3 10.3.1 10.3.2 10.4 10.5 10.6 10.7 10.7.1 10.7.2 10.7.3 10.8 10.9 10.10 10.10.1 10.10.2 10.11 10.12 10.13 10.14 10.14.1 10.14.2 10.14.3 10.15 10.16 11 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 13 General description. . . . . . . . . . . . . . . . . . . . . 13 Serial interface (SPI). . . . . . . . . . . . . . . . . . . . 13 Protocol description . . . . . . . . . . . . . . . . . . . . 13 SPI timing description . . . . . . . . . . . . . . . . . . . 14 Detailed descriptions of registers . . . . . . . . . . 15 Registers detailed description . . . . . . . . . . . . 17 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Dual-port mode. . . . . . . . . . . . . . . . . . . . . . . . 21 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 21 Input clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Quadrature modulator and NCO. . . . . . . . . . . 26 NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 26 Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 26 Minus 3 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DAC transfer function . . . . . . . . . . . . . . . . . . . 27 Full-scale current . . . . . . . . . . . . . . . . . . . . . . 27 Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Full-scale current adjustment . . . . . . . . . . . . . 28 Digital offset adjustment . . . . . . . . . . . . . . . . . 29 Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 31 Output configuration . . . . . . . . . . . . . . . . . . . . 32 Basic output configuration . . . . . . . . . . . . . . . 32 DC interface to an AQM . . . . . . . . . . . . . . . . . 32 AC interface to an AQM . . . . . . . . . . . . . . . . . 35 Power and grounding . . . . . . . . . . . . . . . . . . . 35 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 36 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 15 15.1 15.2 15.3 15.4 16 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 40 40 40 40 40 40 41
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2009 Document identifier: DAC1005D650_1

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